Within photovoltaic research, one strives to develop cost-effective solar cells which provide a high efficiency. The costs for producing, for instance, silicon material-based solar cells can be categorized as follows: material costs, which make up the biggest part of overall costs and which are strongly dependent on the quality of the used silicon, which is a function of its grain size; solar cell process costs; and module process costs.
HIT (Heterojunction with Intrinsic Thin-layer) cells are state of the art and were developed to improve the junction properties of the classical heterojunction cell.
U.S. Pat. No. 5,213,628 describes a photovoltaic device including an intrinsic amorphous semiconductor layer formed on a monocrystalline or polycrystalline semiconductor layer of specified conductivity type, on which an amorphous semiconductor layer of the opposite conductivity type is formed.
U.S. Pat. No. 5,066,340 describes a photovoltaic device including a crystalline silicon semiconductor layer of a specified conductivity type material, an amorphous silicon semiconductor layer of the opposite conductivity type, and an intrinsic microcrystalline silicon semiconductor layer between these two layers.
“Porous Silicon as an intermediate layer for thin-film solar cell” to Bilyalov, et al., Solar Energy Materials & Solar Cells, 65 (2001) 477-485, describes the use of a dual porous silicon layer as an intermediate layer for thin-film solar cells. The porous layer has a thickness of 400 to 700 nm and serves as a seeding layer for epitaxial growth of silicon. The dual porous layer can be used for the lift-off process. In both cases, the porous layer is used outside of the active area of the solar cell device. “Transmission electron microscopy investigation of the crystallographic quality of silicon films grown epitaxially on porous silicon” to Jin et al., Journal of Crystal Growth, 212 (2000) 119/127, describes a porous layer having a thickness of 220 nm for the same purpose.
Japanese Patent Application No. 03-235371 describes the use of an intermediate porous layer to reduce the lattice mismatch between a GaAs layer and a Si layer to reduce lattice defects. A porous layer having a thickness of larger than 100 nm is described.
“Study and fabrication of PIN Photodiode by using ZnSe/PS/Si Structure” to Chang et al., IEEE Transactions on Electron Devices, Vol. 47, No. 1, January 2000, describes a photodiode or photodetector based on a compound material (ZnSe) and a porous silicon layer, which is used to allow high quality growth of ZnSe on a Si/porous Si structure.
“Amorphous/porous heterojunction on thin microcrystalline silicon” to Rubino, et al., Journal of Non-Crystalline Solids, 266-269 (2000) 1044-1048, describes the use of a porous layer in a LED device. An amorphous Silicon/porous silicon on microcrystalline silicon structure is disclosed. The porous Si layer is used for photoluminescence (LED), and has a thickness of 400 nm to 1500 nm.